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rev. 4531d?bcd?07/04 features supply voltage up to 40 v r dson typically 0.5 ? at 25c, maximum 1.1 ? at 150c up to 1.5 a output current three high-side and three low-side drivers u sable as single outputs or half bridges capable to switch all kinds of loads such as dc motors, bulbs, resistors, capacitors and inductors pwm capability for each output controlled by external pwm signal no shoot-through current very low quiescent current i s < 5 a in standby mode over total temperature range outputs short-circuit protected selective overtemperature protection for each switch and overtemperature prewarning undervoltage protection various diagnostic functions such as shorted output, open load, overtemperature and power-supply fail detection serial data interface, daisy chain capable, up to 2 mhz clock frequency so16 power package description the t6819/t6829 are fully protected driver interfaces designed in 0.8-m bcdmos technology. they are used to control up to six different loads by a microcontroller in automotive and industrial applications. each of the three high-side and three low-side drivers is capable to drive currents up to 1.5 a. each driver is freely configurable and can be controlled separately from a standard serial data interface. therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. the ic design especially supports the applications of h-bridges to drive dc motors. the capability to control each output with an external pwm signal opens additional applications. protection is guaranteed regarding short-circuit conditions, overtemperature and und- ervoltage. various diagnostic functions and a very low quiescent current in stand-by mode opens a wide range of applications. automotive qualification (protection against conducted interferences, emc protection and 2-kv esd protection) gives added value and enhanced quality for exacting requirements of automotive applications. dual triple dmos output driver with serial input control t6819/t6829 preliminary
2 t6819/t6829 [preliminary] 4531d?bcd?07/04 figure 1. block diagram out1h out2h out3h di clk do cs pwm uv - protection serial interface input register output register h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r s i o l d p s f i n h o v l h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p fault detect gnd gnd vs out1l out2l out3l vcc thermal protection control logic power-on reset n. u. n. u. n. u. n. u. n. u. n. u. gnd pump charge p h 3 p l 3 p h 2 p l 2 p h 1 p l 1 o c s 3 15 2 13 14 4 5 10 8 6 7 12 1 9 16 11 fault detect fault detect fault detect fault detect fault detect
3 t6819/t6829 [preliminary] 4531d?bcd?07/04 pin configuration figure 2. pinning so16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd out1l out3l out3h cs di clk pwm gnd out2l out2h out1h vs vcc do gnd pin description pin symbol function 1gnd t6819: ground; reference potential; internal connection to pin 9 and pin 16; cooling tab t6829: additional connection to heat slug 2 out1l low-side driver output 1; power mos open drain with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; pwm ability 3 out3l low-side driver output 3; see pin 2 4 out3h high-side driver output 3; power mos open source with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; pwm ability 5 cs chip select input; 5-v cmos logic level input with internal pull up; low = serial communication is enabled, high = disabled 6 di serial data input; 5-v cmos logic level input with internal pull down; receives serial data from the control device; di expects a 16-bit control word with lsb being transferred first 7 clk serial clock input; 5-v cmos logic level input with internal pull down; controls serial data input interface and internal shift register (f max = 2 mhz) 8 pwm pwm input; 5-v cmos logic level input with internal pull down; receives pwm signal to control outputs which are selected for pwm mode by the serial data interface, high = outputs on, low = outputs off 9 gnd ground; see pin 1 10 do serial data output; 5-v cmos logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (lsb is transferred first); output will remain tri-stated unless device is selected by cs = low, therefore, several ics can operate on one data-output line only. 11 vcc logic supply voltage (5 v) 12 vs power supply for high-side output stages out1h, out2h, out3h, internal supply 13 out1h high-side driver output 1; see pin 4 14 out2h high-side driver output 2; see pin 4 15 out2l low-side driver output 2; see pin 2 16 gnd ground; see pin 1
4 t6819/t6829 [preliminary] 4531d?bcd?07/04 functional description serial interface data transfer starts with the falling edge of the cs signal. data must appear at di syn- chronized to clk and are accepted on the falling edge of the clk signal. lsb (bit 0, srr) has to be transferred first. execution of new input data is enabled on the rising edge of the cs signal. when cs is high, pin do is in tri-state condition. this output is enabled on the falling edge of cs. output data will change their state with the rising edge of clk and stay stable until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3. data transfer srr ls1 hs1 ls2 hs2 ls3 hs3 pl1 ph1 pl2 ph2 pl3 ph3 old ocs si cs di clk do tp s1l s1h s2l s2h s3l s3h n. u. n. u. n. u. n. u. n. u. n. u. ovl inh psf 0123456789101112131415 table 1. input data protocol bit input register function 0srr status register reset (high = reset; the bits psf and ovl in the output data register are set to low) 1 ls1 controls output ls1 (high = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 pl1 output ls1 additionally controlled by pwm input 8 ph1 output hs1 additionally controlled by pwm input 9 pl2 see pl1 10 ph2 see ph1 11 pl3 see pl1 12 ph3 see ph1 13 old open load detection (low = on) 14 ocs overcurrent shutdown (high = overcurrent shutdown is active) 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered)
5 t6819/t6829 [preliminary] 4531d?bcd?07/04 table 2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning 1 status ls1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by srr 2 status hs1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by srr 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 ovl over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. bits 1 to 6 can be used to detect the affected switch. (open-load detection bit old = high) 14 inh inhibit: this bit is controlled by software (bit si in input register) high = standby, low = normal operation 15 psf power-supply fail: undervoltage at pin vs detected after power-on reset, the input register has the following status: bit 15 si bit 14 ocs bit 13 old bit 12 ph3 bit 11 pl3 bit 10 ph2 bit 9 pl2 bit 8 ph1 bit 7 pl1 bit 6 hs3 bit 5 ls3 bit 4 hs2 bit 3 ls2 bit 2 hs1 bit 1 ls1 bit 0 srr hhhlllllllllllll the following patterns are used to enable internal test modes of the ic. it is not recommended to use these patterns during normal operation. bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) hhhhhlllllllllll hhhllhhlllllllll hhh llllhhlllllll
6 t6819/t6829 [preliminary] 4531d?bcd?07/04 power-supply fail in case of undervoltage at pin vs, the power-supply fail bit (psf) in the output register is set and all outputs are disabled. to detect an undervoltage, its duration has to last longer than the undervoltage detection delay time t duv . the outputs are enabled immedi- ately when supply voltage recovers normal operation value. the psf bit stays high until it is reset by the srr bit in the input register. open-load detection if the open-load detection bit (old) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detec- tion current i out1-3 ). if the current through the external load does not reach the open- load detection current, the corresponding bit of the output in the output register is set to high. switching on an output stage with old bit set to low disables the open-load function for this output. overtemperature protection if the junction temperature of one ore more output stages exceeds the thermal prewarn- ing threshold, t jpw set , the temperature prewarning bit (tp) in the output register is set. when the temperature falls below the thermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16-bit data word. the status of tp is available at pin do with the falling edge of cs. after the microcontroller has read this information, cs is set high and the data transfer is interrupted without affecting the status of input and output registers. if the junction temperature of an output stage exceeds the thermal shutdown threshold, t j switch off , the affected output is disabled and the corresponding bit in the output register is set to low. additional the overload detection bit (ovl) in the output register is set. the output can be enabled again when the temperature falls below the thermal shutdown threshold, t jswitch on and the srr bit in the input register is set to high. hysteresis of ther- mal prewarning and shutdown threshold avoids oscillations. short-circuit protection the output currents are limited by a current regulator. overcurrent detection is activated by writing a high to the ocs bit in the input register. when the current in an output stage exceeds the overcurrent limitation and shut-dow n threshold, it is switched off after a delay time (t dsd ). the over-load detection bit (ovl) is set and the corresponding status bit in the output register is set to low. for ocs = low the overcurrent shutdown is inac- tive and the ovl bit is not set by an overcurrent. by writing a high to the srr bit in the input register the ovl bit is reset and the disabled outputs are enabled. inhibit the si bit in the input register has to be set to zero to inhibit the t6819/t6829. all output stages are then turned off but the serial interface stays active. the current consumption is reduced to less than 5 a at pin vs and less than 100 a at pin vcc. the output stages can be activated again by bit si = 1.
7 t6819/t6829 [preliminary] 4531d?bcd?07/04 thermal resistance note: 1. threshold for undervoltage detection. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . all values refer to gnd pins. parameters pin symbol value unit supply voltage 12 v vs -0.3 to +40 v supply voltage t < 0.5 s; i s > -2 a 12 v vs -1 v logic supply voltage 11 v vcc -0.3 to +7 v logic input voltage 5 to 8 v cs , v di , v clk , v pwm -0.3 to v vcc + 0.3 v logic output voltage 10 v do -0.3 to v vcc + 0.3 v input current 5 to 8 i cs , i di , i clk , i pwm -10 to +10 ma output current 10 i do -10 to +10 ma output current 2 to 4 13 to 15 i out3h , i out2h, i out1h i out3l , i out2l, i out1l internally limited, see output specification output voltage 2 to 4 13 to 15 i out3h , i out2h, i out1h i out3l , i out2l, i out1l -0.3 to +40 v reverse conducting current (t pulse = 150 s) 2 to 4 13 to 15 towards pin 12 i out3h , i out2h, i out1h i out3l , i out2l, i out1l 17 a junction temperature range t j -40 to +150 c storage temperature range t stg -55 to +150 c parameters test conditions symbol value unit t6819 junction pin measured to gnd pins 1, 9 and 16 r thjp 30 k/w junction ambient r thja 65 k/w t6829 junction pin measured to heat slug gnd pins 1, 9 and 16 r thjp 5 k/w junction ambient r thja 30 k/w operating range parameters symbol value unit supply voltage v vs v uv (1) to 40 v logic supply voltage v vcc 4.75 to 5.25 v logic input voltage v cs ,v di , v clk , v pwm -0.3 to v vcc v serial interface clock frequency f clk 2 mhz pwm input frequency f pwm 1 khz junction temperature range t j -40 to +150 c
8 t6819/t6829 [preliminary] 4531d?bcd?07/04 noise and surge immunity note: 1. test pulse 5: v smax = 40 v. parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) esd s 5.1 2 kv esd (machine model) jedec a115a 200 v electrical characteristics 7.5 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; -40 c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current vs v vs < 20 v, si = low 12 i vs 1 5 a a 1.2 quiescent current vcc 4.75 v < v vcc < 5.25 v, si = low 11 i vcc 60 100 a a 1.3 supply current vs v vs < 20 v normal operating, all outputs off, input register bit 13 (old) = high 12 i vs 4 6 ma a 1.4 supply current vcc 4.75 v < v vcc < 5.25 v, normal operating 11 i vcc 350 650 a a 1.5 discharge current vs v vs = 32.5 v, inh = low 12 i vs 0.5 5.5 ma a 1.6 discharge current vs v vs = 40 v, inh = low 12 i vs 2.5 10 ma a 2 undervoltage detection, power-on reset 2.1 power-on reset threshold 11 v vcc 3.2 3.9 4.4 v a 2.2 power-on reset delay time after switching on v cc t dpor 30 95 190 s a 2.3 undervoltage-detection threshold v cc =5v 12 v uv 5.6 7.0 v a 2.4 undervoltage-detection hysteresis v cc = 5 v 12 ? v uv 0.6 v a 2.5 undervoltage-detection delay time t duv 10 40 s a 3 thermal prewarning and shutdown 3.1 thermal prewarning set t jpw set 120 145 170 c b 3.2 thermal prewarning reset t jpw reset 105 130 155 c b 3.3 thermal prewarning hysteresis ? t jpw 15 k b 3.4 thermal shutdown off t j switch off 150 175 200 c b *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
9 t6819/t6829 [preliminary] 4531d?bcd?07/04 3.5 thermal shutdown on t j switch on 135 160 185 cb 3.6 thermal shutdown hysteresis ? t j switch off 15 k b 3.7 ratio thermal shutdown off/thermal prewarning set t j switch off/ t jpw set 1.05 1.2 b 3.8 ratio thermal shutdown on/thermal prewarning reset t j switch on/ t jpw reset 1.05 1.2 b 4 output specification (out1-out3) 4.1 on resistance i out 1-3 h = -1.3 a 4, 13, 14 r dson1-3h 1.1 ? a 4.2 i out 1-3 l = 1.3 a 2, 3, 15 r dson1-3l 1.1 ? a 4.3 high-side output leakage current v out 1-3 h = 0 v , output stages off 4, 13, 14 i out1-3h -5 a a 4.4 low-side output leakage current v out 1-3 l = v vs, output stages off 2, 3, 15 i out1-3l 5 a a 4.5 high-side switch reverse diode forward voltage i out = 1.5 a 4, 13, 14 v out1-3 - v vs 1.5 v a 4.6 low-side switch reverse diode forward voltage i out 1-3 l = -1.5 a 2, 3, 15 v out1-3l -1.5 v a 4.7 high-side overcurrent limitation and shutdown threshold 4, 13, 14 i out1-3h -2.5 -2 -1.5 a a 4.8 low-side overcurrent limitation and shutdown threshold 2, 3, 15 i out1-3l 1.5 2 2.5 a a 4.9 overcurrent shutdown delay time t dsd 10 40 s a 4.10 high-side open load detection current input register bit 13 (old) = low, output off 4, 13, 14 i out1-3h -2.5 -0.2 ma a 4.11 low-side open load detection current input register bit 13 (old) = low, output off 2, 3, 15 i out1-3l 0.2 2.5 ma a 4.12 high-side output switch on delay (1),(2) v vs = 13 v r load =30 ? t don 20 s a 4.13 low-side output switch on delay (1),(2) v vs = 13 v r load =30 ? t don 20 s a 4.14 high-side output switch off delay (1),(2) v vs =13 v r load = 30 ? t doff 20 s a electrical characteristics (continued) 7.5 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; -40 c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
10 t6819/t6829 [preliminary] 4531d?bcd?07/04 4.15 low-side output switch off delay (1),(2) v vs =13 v r load = 30 ? t doff 3sa 4.16 dead time between corresponding high- and low-side switches v vs =13 v r load = 30 ? t don - t doff 1 s a 4.17 ? t dpwm low-side switch (3) v vs = 13 v r load = 30 ? ? t dpwm = t don - t doff 20 s a 4.18 ? t dpwm high-side switch (3) v vs = 13 v r load = 30 ? ? t dpwm = t don - t doff 3 7 s a 5 logic inputs di, clk, cs, pwm 5.1 input voltage low-level threshold 5-8 v il 0.3 v vcc v a 5.2 input voltage high-level threshold 5-8 v ih 0.7 v vcc v a 5.3 hysteresis of input voltage 5-8 ? v i 50 700 mv a 5.4 pull-down current pins di, clk, pwm v di , v clk, v pwm = v cc 6, 7, 8 i pd 10 65 a a 5.5 pull-up current pin cs v cs = 0 v 5 i pu -65 -10 a a 6 serial interface ? logic output do 6.1 output-voltage low level i dol = 2 ma 10 v dol 0.4 v a 6.2 output-voltage high level i dol = -2 ma 10 v doh v vcc - 0.7 v v a 6.3 leakage current (tri-state) v cs = v cc 0v < v do < v vcc 10 i do -10 10 a a 7 inhibit input ? timing 7.1 delay time from standby to normal operation t dinh 100 s a electrical characteristics (continued) 7.5 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; -40 c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
11 t6819/t6829 [preliminary] 4531d?bcd?07/04 serial interface ? timing no. parameters test conditions pin timing chart no. (1) symbol min. typ. max. unit type* 8.1 do enable after cs falling edge c do = 100 pf 10 1 t endo 200 ns d 8.2 do disable after cs rising edge c do = 100 pf 10 2 t disdo 200 ns d 8.3 do fall time c do = 100 pf 10 - t dof 100 ns d 8.4 do rise time c do = 100 pf 10 - t dor 100 ns d 8.5 do valid time c do = 100 pf 10 10 t doval 200 ns d 8.6 cs setup time 5 4 t cssethl 225 ns d 8.7 cs setup time 5 8 t cssetlh 225 ns d 8.8 cs high time 5 9 t csh 500 ns d 8.9 clk high time 7 5 t clkh 225 ns d 8.10 clk low time 7 6 t clkl 225 ns d 8.11 clk period time 7 - t clkp 500 ns d 8.12 clk setup time 7 7 t clksethl 225 ns d 8.13 clk setup time 7 3 t clksetlh 225 ns d 8.14 di setup time 6 11 t diset 40 ns d 8.15 di hold time 6 12 t dihold 40 ns d *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. see figure 4 on page 12
12 t6819/t6829 [preliminary] 4531d?bcd?07/04 figure 4. serial interface timing with chart number cs do 1 2 cs clk 4 5 6 7 9 8 3 di clk do 10 12 11 inputs di, clk, cs: high level = 0.7 v cc , low level = 0.3 v cc output do: high level = 0.8 v cc , low level = 0.2 v cc
13 t6819/t6829 [preliminary] 4531d?bcd?07/04 application circuit application notes it is strongly recommended to connect the blocking capacitors at v cc and v s as close as possible to the power supply and gnd pins. recommended value for capacitors at v s : electrolytic capacitor c > 22 f in parallel with a ceramic capacitor c = 100 nf. value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current i out1,2,3 (see ?absolute maximum ratings? on page 7). recommended value for capacitors at v cc : electrolytic capacitor c > 10 f in parallel with a ceramic capacitor c = 100 nf. to reduce thermal resistance it is recommended to place cooling areas on the pcb as close as possible to the gnd pins. negative spikes at the output pins (e.g. ne gative spikes caused by an inductive load switched off with a high side driver) may acti vate the overtemperature protection func- tion of the t6819/t6829. in this condition, the affected output will be switched off. if this behavior is not acceptable or compatible with the specific application functionally, it is necessary, that for switching on required outputs again, the srr bit ( s tatus r egister r eset) is set, to ensure a reset of the overtemperature function. v cc 5 v + + 0 to 40 v v s + v batt v cc out1h out2h out3h di clk do cs pwm uv - protection serial interface input register output register h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r s i o l d p s f i n h o v l h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p fault detect gnd gnd vs out1l out2l out3l vcc thermal protection control logic power-on reset n. u. n. u. n. u. n. u. n. u. n. u. gnd pump charge p h 3 p l 3 p h 2 p l 2 p h 1 p l 1 o c s 3 15 2 13 14 4 5 10 8 6 7 12 1 9 16 11 fault detect fault detect fault detect fault detect fault detect mm microcontroller u5021m watchdog v cc reset trigger
14 t6819/t6829 [preliminary] 4531d?bcd?07/04 package information ordering information extended type number package remarks T6819-TBS so16 power package, tubed t6819-tbq so16 power package, taped and reeled t6829-t3s so16 power package with heat slug, tubed t6829-t3q so16 power package with heat slug, taped and reeled technical drawings according to din specifications package so16 dimensions in mm 10.0 9.85 8.89 0.4 1.27 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2 16 9 18
15 t6819/t6829 [preliminary] 4531d?bcd?07/04 revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. changes from rev. 4531c - 04/04 to rev. 4531d - 07/04 1. table ?ordering information? on page 14 changed.
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